/*
 * Copyright (c) 2006-2018, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2018-11-5      balanceTWK   change to new framework
 */

#ifndef __BOARD_H__
#define __BOARD_H__

#include <rtthread.h>
#include "gd32e10x.h"

#include "usart.h"
#include "systick.h"
#include "dma.h"
#include "spi.h"

#define GD32_SRAM_START_ADDRESS     ((uint32_t)0x20000000)
#define GD32_SRAM_SIZE              (32 * 1024)
#define GD32_SRAM_END               ((uint32_t)(GD32_SRAM_START_ADDRESS + GD32_SRAM_SIZE))

#define GD32_FLASH_START_ADDRESS    ((uint32_t)0x08000000)
#define GD32_FLASH_SIZE             (128 * 1024)
#define GD32_FLASH_END_ADDRESS      ((uint32_t)(GD32_FLASH_START_ADDRESS + GD32_FLASH_SIZE))

#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN      (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN      (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN      (&__bss_end)
#endif

#define HEAP_END        GD32_SRAM_END

void SystemClock_Config(void);

#endif
